PCI stands for "peripheral component interface" defined by the PCI Special Interest Group in an effort to stem development of various local bus architectures. PCI bus communications include transactions between "master" and "slave" devices connected to the bus. The prior art is familiar with PCI bus architectures and master-slave communication protocols.
The prior art is also familiar with PCI bridge chips that connect together two PCI buses. These bridge chips can be used, for example, in transferring data from an initiating PCI bus to a target PCI bus. One prior art bridge chip is the DEC21154 chip from Intel, for example. These prior art bridge chips generally provide for sequential transfer of large bursts of data across the bridge.
FIG. 1 shows a prior art PCI bridge chip 10 connected between two PCI buses P1 and P2 in a dual PCI bus system 8. As known in the art, host CPU 14 (e.g., a central processing computer board with a Pentium microprocessor) can connect to the PCI bus P1 through its north-bridge chip set 14a, as shown. One exemplary chip set 14a, for example, is the Intel 440LX chip set. The PCI bridge chip 10 can also include a system accelerator 10b, and can connect to SDRAM 10a, used to store large burst data from the bridge 10.
Various devices can also connect to the PCI buses P1, P2. By way of example, devices S1 and S2 connect, respectively, to PCI bus P1 and P2 and the chip set 14a can drive the devices S1 and S2 across the buses P1, P2. Devices S1, S2 can for example be SCSI or Fibre Channel chips which interface to a storage bus 18 (typically either SCSI or Fibre Channel), as shown. Storage devices typically connect to SCSI buses 18, as illustrated by SCSI device 16 connected to bus P2. SCSI device 16 interfaces to SCSI bus 18 which connects to disk drive 19. In a typical example, the host CPU 14 issues a write command to the device 16 from primary PCI bus P1 to secondary PCI bus P2 through bridge chip 10. FIG. 1 also shows a south-bridge chip set 14b which connects to ISA bus 21, as known in the art.
Standard PCI buses P1 and P2 provide a 32-bit, 33 MHz interface. Later generation chip sets 14 however support 66 MHz processing speeds. Faster bus speeds such as 66 MHz are thus desirable to support the newer chip sets 14 and to increase overall system processing power. However, higher bus speeds present problems in prior art systems such as system 8: as the bus speed increases, the number of devices (e.g., devices S1, S2, 16) connected to the buses P1, P2 must decrease. For example, at 33 MHz, ten devices can connect to the buses P1, P2; yet only four devices can connect to the buses P1, P2 at 66 MHz bus speeds. Accordingly, 66 MHz is not possible for buses P1 and P2, as illustrated in FIG. 1, since there are too many devices connected to the buses.
This problem associated with increasing PCI bus speed affects a variety of PCI bus systems and controllers, including the RAID (Redundant Array of Inexpensive or Independent Disks) controller. A host server typically connects to the RAID controller via a SCSI (Small Computer System Interface) interface; and the bridge chip connects between dual PCI buses within the controller. One of the PCI buses provides connectivity to dual SCSI devices coupled to external disk drives functioning as the RAID storage. In that most RAID cache controllers of the prior art use the system PCI bus to handle data traffic, the bus is shared by many devices, reducing the rate of transfer between the host server CPU (central processing unit) and the RAID controller.
FIG. 1A illustrates the problem further by showing one prior art RAID cache controller 20. The controller 20 includes PCI interfaces 22a, 22b, which connect, respectively, to PCI buses 24a and 24b. Interfaces 22 route data onto appropriate internal buses 26, 28 within the controller 20 according to PCI addressing. For example, interface 22 can route command data onto bus 26 and into PCI bridge 30 (e.g., bridge chip 10, FIG. 1); while routing burst data onto bus 28, through the system accelerator 32 and into SDRAM 20a, e.g., SDRAM 10a, FIG. 1. The architecture of controller 20 illustrates the competition which occurs on the PCI bus between (a) communication from the host chip set, e.g., chip set 14a, FIG. 1, to the controller's accelerator 32 and RAM 20a and (b) inter-PCI bus communication between the chip set and the target PCI bus, e.g., bus 24a to bus 24b communication.
One object of the invention is thus to provide a high speed processor-independent interface between a host CPU and its RAID controller. Another object of the invention is to provide systems and methods for isolating the RAID controller's PCI buses from the CPU's chip set to operate at higher bus speeds, even if the chip set's PCI bus operates at a lower bus speed. Yet another object of the invention is to provide a RAID cache controller which eliminates the above-mentioned bus competition problems. These and other objects will become apparent in the description that follows.